The present invention relates to the field of integrated circuits, and, more particularly, to power devices such as MOS-gated transistors.
Semiconductor devices in the form of integrated circuits are widely used in most electronic devices. For example, computers, cellular telephones, and other similar devices typically include one or more integrated circuits (ICs). In addition, many typical types of ICs are based upon metal oxide semiconductor (MOS) technology wherein each transistor includes doped source and drain regions in a semiconductor substrate, with a well or channel region between the drain and source.
One particular configuration of MOS field effect transistor (FET) which is commonly used for high power applications is the so-called trench MOSFET. In this configuration, a semiconductor layer is formed on a substrate and doped to form a well region on a surface of the semiconductor layer opposite the substrate. Trenches are etched in the well region, usually down to the semiconductor layer, to define several body portions or pillars that extend outward from the semiconductor layer. A MOS-gated device is formed in the trenches which includes an oxide layer adjacent the trench and a corresponding portion of the semiconductor layer, and a conductive layer (e.g., polysilicon) adjacent the oxide layer. Source regions are doped on the surfaces of the pillars, and the substrate and semiconductor layer define a drain region. Channel regions will extend between the source regions and the drain region.
While the configuration of power MOSFETs makes them well suited for handling large amounts of power, a drawback of typical power MOSFET devices is that a high electric field tends to form at the trench bottoms, i.e., near the junction between the gate oxide layer and the semiconductor layer. This field may result in a failure of the oxide due to hot carrier injection, which is commonly referred to as hot carrier aging.
One prior art attempt to address this problem is found in U.S. Pat. No. 6,084,264 to Darwish et al. entitled xe2x80x9cTrench MOSFET Having Improved Breakdown and On-Resistance Characteristics.xe2x80x9d The patent discloses a trench MOSFET including a P-type epitaxial layer overlaying an N+ substrate. An N-type drain region is implanted at the bottom of the trench into the epitaxial layer and is diffused to extend from the bottom of the trench to the substrate. As such, a junction is created between the drain region and the epitaxial layer that extends from the trench to the substrate. Yet, this structure may be disadvantageous in that the dopant used to form the drain regions must extend well beyond the trench bottoms to reach the substrate. That is, it may be difficult to provide the implantation energies and dosages required to form such drain regions due to the carrier scattering inherent in the implantation process. The carrier scattering may result in the trench sidewalls being implanted with a dopant of the wrong polarity, which in turn may nonuniformly lower device threshold and cause short channel effects.
In view of the foregoing background, it is therefore an object of the invention to provide an integrated circuit device that is less susceptible to hot carrier aging.
This and other objects, features, and advantages in accordance with the present invention are provided by an integrated circuit device including a semiconductor layer of a first conductivity type, a plurality of spaced apart semiconductor pillars extending outwardly from said semiconductor layer and defining trenches therebetween, a respective gate structure in each trench, and at least one deep well region having the second conductivity type and being positioned to extend in semiconductor layer between an adjacent pair of corresponding semiconductor pillars and beneath a bottom of at least one trench defining therein at least one inactive gate structure. Each semiconductor pillar may be of a second conductivity type opposite the first conductivity type. The at least one deep well region may be positioned so that at least one trench does not include a deep well region therebeneath to define at least one active gate structure. The at least one deep well region significantly reduces the occurrence of a high electric field at the bottoms of the active gate structures and thereby reduces hot carrier injection into the gate oxide layers.
The device may include a plurality of deep well regions arranged to define alternating active and inactive gate structures. Each semiconductor pillar comprises an upper portion having the first conductivity type, and at least one inactive gate structure may be connected to the upper portion of each semiconductor pillar. At least one inactive gate structure and the at least one active gate structure may be connected together.
Each gate structure may include a gate oxide layer adjacent the trench and a conducting layer, such as a polysilicon layer, adjacent the oxide layer. Furthermore, a semiconductor substrate may be included adjacent the semiconductor layer on a side thereof opposite the semiconductor pillars. The semiconductor substrate may include silicon and may also be more heavily doped than the semiconductor layer. The semiconductor substrate may be of the first conductivity type to thereby define a metal oxide semiconductor field effect transistor or of a second conductivity type to thereby define an insulated gate bipolar transistor, for example. The first conductivity type may be N-type and the second conductivity type may be P-type, for example.
A method for making an integrated circuit device according to the present invention includes forming a plurality of spaced apart semiconductor pillars adjacent a semiconductor layer of a first conductivity type to extend outwardly from the semiconductor layer and define trenches therebetween, forming a respective gate structure in each trench, and forming at least one deep well region having the second conductivity type to extend in the semiconductor layer between an adjacent pair of corresponding semiconductor pillars and beneath a bottom of at least one trench defining therein at least one inactive gate structure. The at least one deep well region may be positioned so that at least one trench does not include a deep well region therebeneath to define at least one active gate structure. Also, each semiconductor pillar may be of a second conductivity type opposite the first conductivity type.